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Sheet目录3862

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2011 Microchip Technology Inc.

DS39932D-page 37

PIC18F46J11 FAMILY

3.0

OSCILLATOR

CONFIGURATIONS

3.1

Overview

Devices in the PIC18F46J11 family incorporate a

different oscillator and microcontroller clock system

than general purpose PIC18F devices.

The PIC18F46J11 family has additional prescalers and

postscalers, which have been added to accommodate

a wide range of oscillator frequencies. Figure 3-1

provides an overview of the oscillator structure.

Other oscillator features used in PIC18 enhanced

microcontrollers, such as the internal oscillator block

and clock switching, remain the same. They are

discussed later in this chapter.

3.1.1

OSCILLATOR CONTROL

The operation of the oscillator in PIC18F46J11 family

devices is controlled through three Configuration regis-

ters and two control registers. Configuration registers,

CONFIG1L, CONFIG1H and CONFIG2L, select the

oscillator mode, PLL prescaler and CPU divider

options. As Configuration bits, these are set when the

device is programmed and left in that configuration until

the device is reprogrammed.

The OSCCON register (Register 3-2) selects the Active

Clock mode; it is primarily used in controlling clock

switching in power-managed modes. Its use is

discussed in Section 3.3.1 “Oscillator Control

Register”

The OSCTUNE register (Register 3-1) is used to trim the

INTOSC frequency source and select the low-frequency

clock source that drives several special features. The

OSCTUNE register is also used to activate or disable the

Phase Locked Loop (PLL). Its use is described in

Section 3.2.5.1 “OSCTUNE Register”

3.2

Oscillator Types

PIC18F46J11 family devices can be operated in eight

distinct oscillator modes. Users can program the

FOSC<2:0> Configuration bits to select one of the

modes listed in Table 3-1. For oscillator modes which

produce a clock output (CLKO) on pin RA6, the output

frequency will be one fourth of the peripheral clock

frequency. The clock output stops when in Sleep mode,

but will continue during Idle mode (see Figure 3-1).

TABLE 3-1:

OSCILLATOR MODES

Mode

Description

ECPLL

External Clock Input mode, the PLL can

be enabled or disabled in software,

CLKO on RA6, apply external clock

signal to RA7.

External Clock Input mode, the PLL is

always disabled, CLKO on RA6, apply

external clock signal to RA7.

HSPLL

High-Speed Crystal/Resonator mode,

PLL can be enabled or disabled in

software, crystal/resonator connected

between RA6 and RA7.

High-Speed Crystal/Resonator mode,

PLL always disabled, crystal/resonator

connected between RA6 and RA7.

INTOSCPLLO Internal Oscillator mode, PLL can be

enabled or disabled in software, CLKO

on RA6, port function on RA7, the

internal oscillator block is used to derive

both the primary clock source and the

postscaled internal clock.

INTOSCPLL Internal Oscillator mode, PLL can be

enabled or disabled in software, port

function on RA6 and RA7, the internal

oscillator block is used to derive both the

primary clock source and the postscaled

internal clock.

INTOSCO

Internal Oscillator mode, PLL is always

disabled, CLKO on RA6, port function on

RA7, the output of the INTOSC

postscaler serves as both the postscaled

internal clock and the primary clock

source.

INTOSC

Internal Oscillator mode, PLL is always

disabled, port function on RA6 and RA7,

the output of the INTOSC postscaler

serves as both the postscaled internal

clock and the primary clock source.

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